Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
G
gr-bladeRF-cdc
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Releases
Package registry
Model registry
Operate
Environments
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
GitLab community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
ELEN90089 CDC
gr-bladeRF-cdc
Commits
598956e8
Commit
598956e8
authored
Jun 6, 2021
by
Sergey Musikhin
Browse files
Options
Downloads
Patches
Plain Diff
fpga_reload flag
parent
65b35193
Branches
Branches containing commit
No related tags found
No related merge requests found
Changes
2
Show whitespace changes
Inline
Side-by-side
Showing
2 changed files
grc/gen_bladerf_blocks.py
+46
-15
46 additions, 15 deletions
grc/gen_bladerf_blocks.py
lib/bladerf/bladerf_common.cc
+2
-2
2 additions, 2 deletions
lib/bladerf/bladerf_common.cc
with
48 additions
and
17 deletions
grc/gen_bladerf_blocks.py
+
46
−
15
View file @
598956e8
...
...
@@ -58,37 +58,57 @@ parameters:
dtype: real
default: samp_rate
- id: fpga_reload
label:
'
FPGA reload
'
category: Advanced
dtype: enum
default: auto
options: [
'
False
'
,
'
True
'
]
hide: part
- id: fpga_image
category: Advanced
label:
'
FPGA image
'
dtype: string
hide: ${
'
$
'
}{
'
none
'
if fpga_reload ==
'
True
'
else
'
part
'
}
- id: power_monitoring
label:
'
Enable power monitoring
'
dtype: bool
category: Advanced
label:
'
Power monitoring
'
dtype: enum
default: False
options: [False, True]
option_labels: [
'
Disable
'
,
'
Enable
'
]
- id: ref_clk
category: Advanced
label:
'
Reference clock
'
dtype: real
- id: in_clk
category: Advanced
label:
'
Input clock
'
dtype: enum
default: auto
options: [
'
ONBOARD
'
,
'
EXTERNAL
'
]
option_labels: [
'
O
NBOARD
'
,
'
EXTERNAL
'
]
option_labels: [
'
O
nboard
'
,
'
External
'
]
- id: out_clk
category: Advanced
label:
'
Output clock
'
dtype:
bool
dtype:
enum
default: False
options: [False, True]
option_labels: [
'
Disable
'
,
'
Enable
'
]
- id: dac
category: Advanced
label:
'
VCXTO DAC
'
dtype: real
default: 10000
- id: xb200
category: Advanced
label:
'
XB-200
'
dtype: enum
default: auto
...
...
@@ -128,6 +148,7 @@ templates:
+
"
,bladerf=
"
+ str(${
'
$
'
}{device_id})
+
"
,verbosity=
"
+
'
${
'
$
'
}{verbosity}
'
+
"
,fpga=
"
+ str(${
'
$
'
}{fpga_image})
+
"
,fpga-reload=
"
+
'
${
'
$
'
}{fpga_reload}
'
+
"
,power_monitoring=
"
+ str(${
'
$
'
}{power_monitoring})
+
"
,ref_clk=
"
+ str(${
'
$
'
}{ref_clk})
+
"
,in_clk=
"
+
'
${
'
$
'
}{in_clk}
'
...
...
@@ -250,32 +271,37 @@ file_format: 1
PARAMS_TMPL
=
"""
- id: freq${n}
label:
'
Ch${n}: Center frequency (Hz)
'
category:
'
Channel ${n}
'
label:
'
Center frequency (Hz)
'
dtype: real
default: 1e8
hide: ${
'
$
'
}{
'
none
'
if (nchan > ${n}) else
'
all
'
}
- id: corr${n}
label:
'
Ch${n}: Frequency Correction (ppm)
'
category:
'
Channel ${n}
'
label:
'
Frequency Correction (ppm)
'
dtype: real
default: 0
hide: ${
'
$
'
}{
'
none
'
if (nchan > ${n}) else
'
all
'
}
- id: bw${n}
label:
'
Ch${n}: Bandwidth (Hz)
'
category:
'
Channel ${n}
'
label:
'
Bandwidth (Hz)
'
dtype: real
default: 200000
hide: ${
'
$
'
}{
'
none
'
if (nchan > ${n}) else
'
all
'
}
- id: bias_tee${n}
label:
'
Ch${n}: Bias tee
'
category:
'
Channel ${n}
'
label:
'
Bias tee
'
dtype: bool
default: False
hide: ${
'
$
'
}{
'
none
'
if (nchan > ${n}) else
'
all
'
}
% if sourk ==
'
source
'
:
- id: dc_offset_mode${n}
label:
'
Ch${n}: DC Offset Mode
'
category:
'
Channel ${n}
'
label:
'
DC Offset Mode
'
dtype: int
default: 0
options: [0, 1, 2]
...
...
@@ -283,7 +309,8 @@ PARAMS_TMPL = """
hide: ${
'
$
'
}{
'
none
'
if (nchan > ${n}) else
'
all
'
}
- id: iq_balance_mode${n}
label:
'
Ch${n}: IQ Balance Mode
'
category:
'
Channel ${n}
'
label:
'
IQ Balance Mode
'
dtype: int
default: 0
options: [0, 1, 2]
...
...
@@ -291,7 +318,8 @@ PARAMS_TMPL = """
hide: ${
'
$
'
}{
'
none
'
if (nchan > ${n}) else
'
all
'
}
- id: gain_mode${n}
label:
'
Ch${n}: Gain Mode
'
category:
'
Channel ${n}
'
label:
'
Gain Mode
'
dtype: bool
default: False
options: [False, True]
...
...
@@ -300,19 +328,22 @@ PARAMS_TMPL = """
% endif
- id: gain${n}
label:
'
Ch${n}: RF Gain (dB)
'
category:
'
Channel ${n}
'
label:
'
RF Gain (dB)
'
dtype: real
default: 10
hide: ${
'
$
'
}{
'
none
'
if (nchan > ${n}) else
'
all
'
}
- id: if_gain${n}
label:
'
Ch${n}: IF Gain (dB)
'
category:
'
Channel ${n}
'
label:
'
IF Gain (dB)
'
dtype: real
default: 20
hide: ${
'
$
'
}{
'
none
'
if (nchan > ${n}) else
'
all
'
}
- id: bb_gain${n}
label:
'
Ch${n}: BB Gain (dB)
'
category:
'
Channel ${n}
'
label:
'
BB Gain (dB)
'
dtype: real
default: 20
hide: ${
'
$
'
}{
'
none
'
if (nchan > ${n}) else
'
all
'
}
...
...
This diff is collapsed.
Click to expand it.
lib/bladerf/bladerf_common.cc
+
2
−
2
View file @
598956e8
...
...
@@ -222,10 +222,10 @@ void bladerf_common::init(dict_t const &dict, bladerf_direction direction)
/* Load a FPGA */
if
(
dict
.
count
(
"fpga"
))
{
if
(
dict
.
count
(
"fpga-reload"
)
==
0
&&
if
(
(
dict
.
count
(
"fpga-reload"
)
==
0
||
_get
(
dict
,
"fpga-reload"
)
==
"False"
)
&&
bladerf_is_fpga_configured
(
_dev
.
get
())
==
1
)
{
BLADERF_WARNING
(
"FPGA is already loaded. Set fpga-reload=
1
to force a "
BLADERF_WARNING
(
"FPGA is already loaded. Set fpga-reload=
False
to force a "
"reload."
);
}
else
{
std
::
string
fpga
=
_get
(
dict
,
"fpga"
);
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment